1. Field of the Invention
The present invention relates to semiconductor device fabrication and, in particular, to processes for forming implanted regions during semiconductor device fabrication.
2. Description of the Related Art
The fabrication of semiconductor devices often involves the processing of a semiconductor substrate (e.g. a silicon wafer) through a series of steps. Typically, this series of steps includes multiple ion implantation processes during which dopant atoms are introduced into and beyond the surface of the semiconductor substrate. The dopant atoms are added to the semiconductor substrate to form various semiconductor device regions, such as well regions, source and drain regions, and Lightly Doped Drain (LDD) extension regions. The dopant atoms are also added to modify the electrical characteristics of the semiconductor device, as in the case of Threshold Voltage (V.sub.T) adjust implants. See S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Volume 1--Process Technology, 280-283 (Lattice Press 1986), which is hereby incorporated by reference, for a further discussion of ion implantation processes.
Referring to FIG. 1, a representative conventional MOS transistor structure is illustrated. The MOS transistor structure 10 includes a gate oxide layer 12 overlying P-type semiconductor substrate 14 between N-type LDD source extension region 16 and N-type LDD drain extension region 18. The N-type LDD source extension region 16 extends from an N-type source region 28 in the P-type semiconductor substrate, while the N-type LDD drain extension region 18 extends from an N-type drain region 30. Channel region 20 is located in the P-type semiconductor substrate 14 between the N-type LDD source extension region 16 and the N-type LDD drain extension region 18. A patterned polysilicon gate layer 22 overlies the gate oxide layer 12. Gate sidewall spacers 24 and 26 are formed on the sidewalls of patterned polysilicon gate layer 22 and gate oxide layer 12. The gate sidewall spacers 24 and 26 are typically formed of silicon dioxide or silicon nitride. In MOS transistors with short channel lengths, namely those with channel lengths of less than 0.5 microns, specialized "halo" implant processes are frequently employed to introduce dopant atoms under the N-type LDD source extension region 16 and the N-type LDD drain extension region 18, in order to suppress the Drain-Induced Barrier Lowering (DIBL) effect. The result of such "halo" implant processes is the creation of a halo implant region, such as P-type halo implant region 32, where the P-type doping level is significantly higher than in the surrounding P-type semiconductor substrate.
Halo implant processes are conventionally conducted after the patterned polysilicon gate layer has been formed, but before the formation of the gate sidewall spacers, and therefore employ a high implant angle in order to place the dopant atoms well beneath the patterned polysilicon gate layer. See, S. Wolf, Silicon Processing for the VLSI Era, Volume 3--The Submicron MOSFET, 232 -240, 309-311, 621-622 (Lattice Press 1995), which is hereby incorporated by reference, for a further discussion of halo implant processes. A drawback of conventional halo implant processes is that the implanted dopant atoms are not directly positioned at the optimum location in the semiconductor substrate (i.e. at the lateral edge of the LDD source and drain extension regions in the channel region, as well as at the interface between the gate oxide layer and the channel region) due to blocking (i.e. "shadowing") of the dopant atoms by the patterned polysilicon gate layer. This drawback is typically addressed by implanting a relatively large dose of dopant atoms, while relying on diffusion and scattering to position at least some of the dopant atoms at the optimum location. Such an approach, however, leads to (i) extensive counterdoping of the LDD source and drain extension regions, (ii) degradation of carrier mobility due to dopant atom induced scattering, and (iii) parasitic junction capacitance (i.e. vertical capacitance) between the LDD source and drain extension regions and the halo implant region.
There is, therefore, still a need in the art for a process that provides for the creation of implanted regions at optimum locations underneath a patterned polysilicon gate layer.